TWI Industrial Member Report Summary 675/1999
J M Goward
In electronic packaging of silicon die, current practice is to use surface mount components of various sizes. The problem that large area surface mount components, such as quad flat packs (QFPs) have, is the pitch requirements to connect the peripheral I/Os. As the number of I/Os increases, the pitch must be reduced to accommodate the number of pins that the package has. I/O counts have increased, and component lead pitches have been reduced from 0.5 to 0.3mm, in some cases. The leads can be easily damaged during transit and assembly of the component to the PCB.
The development of the ball grid array (BGA) has allowed area array interconnects to be made, removing the problems associated with fine pitch peripheral leaded components. Ball grid array technologies offer alternative solutions to high density interconnect requirements, using an area array of solder ball connections that can provide packages with 250-1089 I/Os in the same area as a 208 pin QFP. The pitch change, to 1.27mm, alleviates the problems associated with 0.3mm QFPs but adds a further complication. Multi-level substrates, required to allow the I/Os to fan out from the device, are now a prerequisite and more refined inspection techniques to look at the hidden solder joint are needed. Ball grid array assemblies are rapidly gaining favour as the packaging choice for high I/O devices that require improved electrical connectivity.
The objectives of this report are to:
- Review the technology of BGA packages
- Define the advantages and disadvantages of this packaging technology
- Define the assembly and inspections requirements to make sound electrical joints
- Define the potential reliability concerns of this technology.